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Advanced Metal Gate/High-K Dielectric Stacks for High-Performance CMOS Transistors Robert Chau

Components Research, Logic 5200 N.E. Elam Young Parkway, Phone: 503-613-6141. E-mail 1. Abstract We have successfully engineered n-type and p-type metal electrodes with the correct work functions on high-K gate dielectrics for high-performance CMOS applications. The resulting metal gate/high-K dielectric stacks have i) equivalent oxide thickness (EOT) of 1.0nm with negligible gate oxide leakage, ii) desirable transistor threshold voltages for n- and p-channel MOSFETs, and iii) transistor channel mobilities close to those of SiO2. The CMOS transistors fabricated with these advanced metal gate/high-K dielectric stacks achieve the expected high drive current performance. 2. Introduction For more than 15 years the physical thickness of SiO 2 has been aggressively scaled for low-power, high- performance CMOS applications. Figure 1 shows the physical thickness trend of SiO . Recently SiO with 2 2 physical thickness of 1.2nm (see Fig. 2) has been successfully implemented in the 90nm logic node [1]. In addition, SiO2 with physical thickness of 0.8nm (see Fig. 3) has been demonstrated in the laboratory [2-3]. Continual gate oxide scaling, however, will require the use of dielectric materials with higher dielectric constant (K) since i) the gate oxide leakage is increasing with decreasing SiO thickness, and ii) SiO2 is running 2 out of atoms for further scaling. So far the most common high-K dielectric materials investigated by both academia and industry are Hf-based and Zr-based [4-5]. 3. Challenges in Replacing SiO2 with High-K Dielectrics 3a. PolySi/High-K Dielectric Stack There are two typical problems in replacing polySi/SiO2 with the polySi/high-K dielectric stack for high- performance CMOS applications. First, high-K dielectrics and polySi are incompatible due to the Fermi level pinning at the polySi/high-K interface [6], which causes high threshold voltages in MOSFET transistors . The Fermi level pinning is most likely caused by defect formation at the polySi/high-K dielectric interface, as illustrated in Fig. 4. Second, polySi/high-K transistors exhibit severely degraded channel mobility due to the coupling of low energy surface optical (SO) phonon modes arising from the polarization of the high-K dielectric to the inversion channel charge carriers [7-8]. 3b. Metal-gate/High-K Dielectric Stack Metal gate electrodes may be more effective than polySi in screening the high-K SO phonons from coupling to Technology Development, Intel Corporation Hillsboro, OR 97124, USA. Mail-stop: RA3-252 address: robert.s.chau@intel.com the channel under inversion conditions, resulting in improved channel mobility [7-8]. However, the use of high-K/metal-gate require a n-type metal and a p-type metal with the right work functions on the high-K dielectric for high-performance CMOS logic applications on bulk Si [9]. So far, all the metal gate electrodes reported in literature have work functions that are mid-gap or close to mid-gap on high-K dielectrics (e.g. mid-gap TiN [8]), and the resulting CMOS transistors have high threshold voltages and hence poor drive performance. 4. New Metal Gate/High-K Dielectric Stacks to Achieve Record-setting Transistor Performance We have successfully engineered n-type and p-type metal electrodes that have the correct work functions on the high-K for high-performance CMOS, as shown in Fig. 5. The resulting metal gate/high-K dielectric stacks have Read the full Advanced Metal Gate/High-K Dielectric Stacks for High-Performance CMOS Transistors Robert Chau.

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