Intel® Stratix® 10 MX 1650 FPGA

Specifications

Resources

I/O Specifications

Advanced Technologies

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Intel® Stratix® 10 MX 1650 FPGA 1SM16BHU1F53E1VG

  • MM# 985054
  • Spec Code SRETG
  • Ordering Code 1SM16BHU1F53E1VG
  • Stepping B0
  • MDDS Content IDs 706259

Intel® Stratix® 10 MX 1650 FPGA 1SM16BHU1F53E2VG

  • MM# 985055
  • Spec Code SRETH
  • Ordering Code 1SM16BHU1F53E2VG
  • Stepping B0
  • MDDS Content IDs 706259

Intel® Stratix® 10 MX 1650 FPGA 1SM16BHU2F53E1VG

  • MM# 985056
  • Spec Code SRETJ
  • Ordering Code 1SM16BHU2F53E1VG
  • Stepping B0
  • MDDS Content IDs 706259

Intel® Stratix® 10 MX 1650 FPGA 1SM16BHU2F53E2VG

  • MM# 985057
  • Spec Code SRETK
  • Ordering Code 1SM16BHU2F53E2VG
  • Stepping B0
  • MDDS Content IDs 706259

Intel® Stratix® 10 MX 1650 FPGA 1SM16BHU3F53E1VG

  • MM# 985058
  • Spec Code SRETL
  • Ordering Code 1SM16BHU3F53E1VG
  • Stepping B0
  • MDDS Content IDs 706259

Intel® Stratix® 10 MX 1650 FPGA 1SM16BHU3F53E2VG

  • MM# 985059
  • Spec Code SRETM
  • Ordering Code 1SM16BHU3F53E2VG
  • Stepping B0
  • MDDS Content IDs 706259

Intel® Stratix® 10 MX 1650 FPGA 1SM16BHU3F53E3VG

  • MM# 985062
  • Spec Code SRETN
  • Ordering Code 1SM16BHU3F53E3VG
  • Stepping B0
  • MDDS Content IDs 706259

Intel® Stratix® 10 MX 1650 FPGA 1SM16BEU1F55E1VG

Intel® Stratix® 10 MX 1650 FPGA 1SM16BEU1F55E2VG

Intel® Stratix® 10 MX 1650 FPGA 1SM16BEU2F55E1VG

Intel® Stratix® 10 MX 1650 FPGA 1SM16BEU2F55E2VG

Intel® Stratix® 10 MX 1650 FPGA 1SM16BEU3F55E3VG

Intel® Stratix® 10 MX 1650 FPGA 1SM16BEU3F55E2VG

Intel® Stratix® 10 MX 1650 FPGA 1SM16BHU2F53E2VGAS

  • MM# 999GKA
  • Spec Code SRFXE
  • Ordering Code 1SM16BHU2F53E2VGAS
  • Stepping B0
  • MDDS Content IDs 706259

Intel® Stratix® 10 MX 1650 FPGA 1SM16BEU3F55E3VGAS

  • MM# 999GKL
  • Spec Code SRFXL
  • Ordering Code 1SM16BEU3F55E3VGAS
  • Stepping B0
  • MDDS Content IDs 800035

Intel® Stratix® 10 MX 1650 FPGA 1SM16BEU3F55E3VGBK

  • MM# 99A7V2
  • Spec Code SRKDF
  • Ordering Code 1SM16BEU3F55E3VGBK
  • Stepping B0

Intel® Stratix® 10 MX 1650 FPGA 1SM16BHU2F53E2VGBK

  • MM# 99A7W1
  • Spec Code SRKE3
  • Ordering Code 1SM16BHU2F53E2VGBK
  • Stepping B0

Intel® Stratix® 10 MX 1650 FPGA 1SM16BHU1F53E2VGNE

  • MM# 99AKXA
  • Spec Code SRL11
  • Ordering Code 1SM16BHU1F53E2VGNE
  • Stepping B0

Intel® Stratix® 10 MX 1650 FPGA 1SM16BHU2F53E1VGNE

  • MM# 99AKXC
  • Spec Code SRL12
  • Ordering Code 1SM16BHU2F53E1VGNE
  • Stepping B0

Intel® Stratix® 10 MX 1650 FPGA 1SM16BHU2F53E2VGNE

  • MM# 99AKXD
  • Spec Code SRL13
  • Ordering Code 1SM16BHU2F53E2VGNE
  • Stepping B0

Intel® Stratix® 10 MX 1650 FPGA 1SM16BHU3F53E1VGNE

  • MM# 99AKXF
  • Spec Code SRL14
  • Ordering Code 1SM16BHU3F53E1VGNE
  • Stepping B0

Intel® Stratix® 10 MX 1650 FPGA 1SM16BHU3F53E2VGNE

  • MM# 99AKXG
  • Spec Code SRL15
  • Ordering Code 1SM16BHU3F53E2VGNE
  • Stepping B0

Intel® Stratix® 10 MX 1650 FPGA 1SM16BHU3F53E3VGNE

  • MM# 99AKXH
  • Spec Code SRL16
  • Ordering Code 1SM16BHU3F53E3VGNE
  • Stepping B0

Intel® Stratix® 10 MX 1650 FPGA 1SM16BEU1F55E1VGNE

  • MM# 99AKXJ
  • Spec Code SRL17
  • Ordering Code 1SM16BEU1F55E1VGNE
  • Stepping B0

Intel® Stratix® 10 MX 1650 FPGA 1SM16BEU1F55E2VGNE

  • MM# 99AKXK
  • Spec Code SRL18
  • Ordering Code 1SM16BEU1F55E2VGNE
  • Stepping B0

Intel® Stratix® 10 MX 1650 FPGA 1SM16BEU2F55E1VGNE

  • MM# 99AKXL
  • Spec Code SRL19
  • Ordering Code 1SM16BEU2F55E1VGNE
  • Stepping B0

Intel® Stratix® 10 MX 1650 FPGA 1SM16BEU3F55E1VGNE

  • MM# 99AKXM
  • Spec Code SRL1A
  • Ordering Code 1SM16BEU3F55E1VGNE
  • Stepping B0

Intel® Stratix® 10 MX 1650 FPGA 1SM16BEU3F55E3VGNE

  • MM# 99AKXN
  • Spec Code SRL1B
  • Ordering Code 1SM16BEU3F55E3VGNE
  • Stepping B0

Intel® Stratix® 10 MX 1650 FPGA 1SM16BHU1F53E1VGNE

  • MM# 99AL0G
  • Spec Code SRL24
  • Ordering Code 1SM16BHU1F53E1VGNE
  • Stepping B0

Intel® Stratix® 10 MX 1650 FPGA 1SM16BEU2F55E2VGNE

  • MM# 99AL0H
  • Spec Code SRL25
  • Ordering Code 1SM16BEU2F55E2VGNE
  • Stepping B0

Intel® Stratix® 10 MX 1650 FPGA 1SM16BEU3F55E2VGNE

  • MM# 99AL0J
  • Spec Code SRL26
  • Ordering Code 1SM16BEU3F55E2VGNE
  • Stepping B0

Retired and discontinued

Intel® Stratix® 10 MX 1650 FPGA 1SM16CHU1F53E1VG

Intel® Stratix® 10 MX 1650 FPGA 1SM16CHU1F53E2VG

Intel® Stratix® 10 MX 1650 FPGA 1SM16CHU2F53E1VG

Intel® Stratix® 10 MX 1650 FPGA 1SM16CHU2F53E2VG

Intel® Stratix® 10 MX 1650 FPGA 1SM16CHU3F53E1VG

Intel® Stratix® 10 MX 1650 FPGA 1SM16CHU3F53E2VG

Intel® Stratix® 10 MX 1650 FPGA 1SM16CHU3F53E3VG

Intel® Stratix® 10 MX 1650 FPGA 1SM16CHU1F53E1VGNE

  • MM# 99AKXV
  • Spec Code SRL1C
  • Ordering Code 1SM16CHU1F53E1VGNE
  • Stepping B0
  • MDDS Content IDs 809465

Intel® Stratix® 10 MX 1650 FPGA 1SM16CHU1F53E2VGNE

  • MM# 99AKZ6
  • Spec Code SRL1H
  • Ordering Code 1SM16CHU1F53E2VGNE
  • Stepping B0
  • MDDS Content IDs 809465

Intel® Stratix® 10 MX 1650 FPGA 1SM16CHU2F53E1VGNE

  • MM# 99AKZ8
  • Spec Code SRL1J
  • Ordering Code 1SM16CHU2F53E1VGNE
  • Stepping B0
  • MDDS Content IDs 809465

Intel® Stratix® 10 MX 1650 FPGA 1SM16CHU2F53E2VGNE

  • MM# 99AKZ9
  • Spec Code SRL1K
  • Ordering Code 1SM16CHU2F53E2VGNE
  • Stepping B0
  • MDDS Content IDs 809465

Intel® Stratix® 10 MX 1650 FPGA 1SM16CHU3F53E1VGNE

  • MM# 99AL0M
  • Spec Code SRL29
  • Ordering Code 1SM16CHU3F53E1VGNE
  • Stepping B0
  • MDDS Content IDs 809465

Intel® Stratix® 10 MX 1650 FPGA 1SM16CHU3F53E2VGNE

  • MM# 99AL0N
  • Spec Code SRL2A
  • Ordering Code 1SM16CHU3F53E2VGNE
  • Stepping B0
  • MDDS Content IDs 809465

Intel® Stratix® 10 MX 1650 FPGA 1SM16CHU3F53E3VGNE

  • MM# 99AL0P
  • Spec Code SRL2B
  • Ordering Code 1SM16CHU3F53E3VGNE
  • Stepping B0
  • MDDS Content IDs 809465

Trade compliance information

  • ECCN 3A001.A.7.B
  • CCATS G171972
  • US HTS 8542390001

PCN Information

SRFXE

SRL1A

SRL1B

SRL1C

SRETM

SREZS

SRL14

SRETL

SREZR

SRL15

SRETK

SREZQ

SRL16

SRETJ

SREZP

SRL17

SRFXL

SRL18

SRETH

SREZN

SRL19

SRETG

SRL11

SRL12

SRL13

SRKE3

SRL2A

SRL2B

SRL25

SRL26

SRL29

SRETU

SRETT

SRETS

SRETR

SRETQ

SRETP

SRKDF

SRETN

SRL24

SRL1H

SRL1J

SRETV

SRF01

SRL1K

Drivers and Software

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Name

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Maximum High Bandwidth Memory (HBM)

The total capacity of all the in-package high-bandwidth memory stacks in the Intel device or component.
† Actual count could be lower depending on package.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Maximum Pulse-Amplitude Modulation (PAM4) Transceivers

The maximum number of PAM4 transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Pulse-Amplitude Modulation (PAM4) Data Rate

The maximum PAM4 data rate that is supported by the PAM4 transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

Hyper-Registers

Hyper-Registers are additional register bits (flip-flops) located in the interconnect of some Intel FPGA device families, allowing for re-timing and pipelining of the interconnect to enable higher clock frequency in the FPGA fabric.

FPGA Bitstream Security

Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.